1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors in complex circuits including a high speed logic circuitry and functional blocks with less speed-critical behavior, such as a memory area, for instance in the form of a cache memory of a CPU.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel, due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the latter aspect renders the reduction of the channel length, and associated therewith the reduction of the channel resistivity, a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
In view of the former aspect, in addition to other advantages, the silicon-on-insulator (SOI) architecture has been continuously gaining in importance for manufacturing MOS transistors, due to their characteristics of a reduced parasitic capacitance of the PN junctions, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region, in which the drain and source regions as well as the channel region are provided, also referred to as body, is dielectrically encapsulated, which provides significant advantages which, however, also gives rise to a plurality of issues. Contrary to the body of bulk devices, which is electrically connected to the substrate and thus applying a specified potential to the substrate maintains the bodies of bulk transistors at a specified potential, the body of SOI transistors is not connected to a specified reference potential, and, hence, the body's potential may usually float, due to accumulating minority charge carriers, thereby leading to a variation of the threshold voltage Vt of the transistors, which may also be referred to as hysteresis. In particular, for static memory cells, the threshold variation may result in significant instabilities of the cell, which may not be tolerable in view of data integrity of the memory cell. Consequently, in conventional SOI devices including memory blocks, the drive current fluctuations associated with the threshold voltage variations are taken into consideration by appropriate design measures in order to provide a sufficiently high drive current range of the SOI transistors in the memory block. Hence, the respective SOI transistors in the memory block are typically formed with a sufficiently large width so as to provide the required drive current margins, thereby requiring a moderately high amount of chip area. Similarly, other design measures for eliminating threshold fluctuations caused by the floating body potential, for instance so-called body ties, are a very space-consuming solution and may not be desirable for highly scaled and complex semiconductor devices including extended RAM areas.
In view of the above-described situation, there exists a need for an alternative technique that enables the formation of advanced SOI devices in critical functional blocks while avoiding or at least reducing the effects of one or more of the problems identified above.